1. Field of the Invention
The present invention relates generally to a method and apparatus for responding to interrupts. More specifically, it relates to a vectoring scheme in which vectors previously loaded into interrupt registers can be immediately loaded into address counters upon activation of an interrupt and utilized efficiently by a plurality of processors.
2. Description of the Related Art
A number of interrupt schemes are well known in the art. Typical interrupt schemes involve fetching an address vector from a specified location in memory upon activation of interrupt. Interrupt schemes also typically push information onto a stack in memory to save key registers. This way program execution can be restarted at the same memory location at which the program was executing when the interrupt occurred.
In a typical sequence, a processor pushes all current registers onto the stack upon receipt of an interrupt, fetches the interrupt vector from a specified place in memory and executes the interrupt routine. Following execution of the interrupt routine, the information is pulled off the stack and normal execution is resumed.
However, in a system in which interrupts are routinely used to signal the start of a processing function, and in which the response time of the system is limited, the overhead involved in traditional interrupt schemes is excessive. This overhead manifests itself in the number of clock cycles required to go to memory, fetch the correct vector, and load it into the program counter. Accordingly, a more efficient interrupt approach is required to meet the needs of an interrupt driven system with limited time resources.
Additionally, in an environment requiring synchronization of both synchronous and asynchronous routines in a plurality of signal processors, more efficient use of processors is desirable where the processing is intensive and synchronous trigger rates are high. Typical approaches have involved some sort of load and lock to assure correct communication among sequential tasks in a plurality of processors.